MC68HC908LD64 Datasheet, PDF (277/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

On-Screen Display (OSD)
OSD Module I/O Registers
18.7 OSD Module I/O Registers
Seven registers are associated with the OSD module, they outlined in
the following sections.
18.7.1 OSD Control Register (OSDCR)
Address: $0060
Bit 7
6
5
4
3
2
1
0
Read:
OSDMEN R OSDRST CLKINV CLKPH1 CLKPH0 HALFCLK OSDIEN
Write:
Reset: 0
0
0
0
0
0
0
Figure 18-5. OSD Control Register (OSDCR)
OSDMEN — OSD Memory Enable
When this bit is clear, the OSD RAM and font FLASH memory is
directly under CPU access. When OSDMEN is set, OSD circuitry has
read control over the OSD RAM and font FLASH memory for
displaying the contents; CPU access is indirect, by writing to address
and data buffers. The OSDMEN bit should be cleared while no OSD
are displaying. Reset clear this bit.
1 = OSD RAM and font FLASH is under OSD circuitry access
0 = OSD RAM and font FLASH is directly under CPU access
OSDRST — OSD Module Reset
Setting this bit resets the entire OSD logic and row15 registers (row1
to row14 registers are unaffected), and holds the OSD in the reset
state. The input PCLK clock is prevented from entering the OSD
module to reduce power consumption.
Reset clear this bit.
1 = Reset OSD logic and row15 registers
0 = No effect
CLKINV — Pixel Clock Inversion
This bit is set to invert the PCLK input of OSD. Reset clears this bit.
1 = PCLK input inverted
0 = PCLK input not inverted
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
On-Screen Display (OSD)
Data Sheet
277