MC68HC908LD64 Datasheet, PDF (302/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output (I/O) Ports
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx
data latch. When bit DDRBx is a logic 0, reading address $0001 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 19-3 summarizes
the operation of the port B pins.
Table 19-3. Port B Pin Functions
DDRB
Bit
0
PTB Bit
X⁽¹⁾
I/O Pin Mode
Input, Hi-Z⁽²⁾
Accesses to DDRB
Read/Write
DDRB[7:0]
1
X
Output
DDRB[7:0]
Notes:
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect input.
Accesses to PTB
Read
Pin
Write
PTB[7:0]⁽³⁾
PTB[7:0] PTB[7:0]
19.4.3 Port B Options
The PWM control register (PWMCR) selects the port B pins for PWM
function or as standard I/O function. (See Section 12. Pulse Width
Modulator (PWM).)
Address: $0078
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PWM7E PWM6E PWM5E PWM4E PWM3E PWM2E PWM1E PWM0E
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 19-9. PWM Control Register (PWMCR)
PWM7E–PWM0E — PWM Output Enable Bits
Setting a PWMxE bit to logic 1 configures the PTBx/PWMx pin for
PWM output function. Reset clears the PWMxE bits.
1 = PTBx/PWMx pin configured as PWMx interrupt pin
0 = PTBx/PWMx pin configured as PTBx standard I/O pin
Data Sheet
302
Input/Output (I/O) Ports
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor