MC68HC908LD64 Datasheet, PDF (107/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
CGM I/O Registers
Address: $0039
Bit 7
6
5
4
3
2
1
Bit 0
Read:
LOCK
0
0
0
0
AUTO
ACQ
XLD
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-4. PLL Bandwidth Control Register (PBWC)
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control.
When initializing the PLL for manual operation (AUTO = 0), the ACQ
bit should be cleared before turning the PLL on. Reset clears the
AUTO bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set
when the VCO clock CGMVCLK, is locked (running at the
programmed frequency). When the AUTO bit is clear, LOCK reads
as 0 and has no meaning. Reset clears the LOCK bit.
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
ACQ — Acquisition Mode Bit
When the AUTO bit is set, ACQ is a read-only bit that indicates
whether the PLL is in acquisition mode or tracking mode. When the
AUTO bit is clear, ACQ is a read/write bit that controls whether the
PLL is in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written
value from manual operation is stored in a temporary location and is
recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
1 = Tracking mode
0 = Acquisition mode
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
Clock Generator Module (CGM)
Data Sheet
107