MC68HC908LD64 Datasheet, PDF (244/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

DDC12AB Interface
16.6.5 DDC Status Register (DDCSR)
Address: $0019
Bit 7
6
5
4
3
2
1
Read: RXIF TXIF MATCH SRW RXAK SCLIF TXBE
Write: 0
0
0
Reset: 0
0
0
0
1
0
1
= Unimplemented
Figure 16-6. DDC Status Register (DDCSR)
Bit 0
RXBF
0
RXIF — DDC Receive Interrupt Flag
This flag is set after the data receive register (DDCDRR) is loaded
with a new received data. Once the DDCDRR is loaded with received
data, no more received data can be loaded to the DDCDRR until the
CPU reads the data from the DDCDRR to clear RXBF flag. RXIF
generates an interrupt request to CPU if the DIEN bit in DDCCR is
also set. This bit is cleared by writing "0" to it or by reset; or when the
DEN = 0.
1 = New data in data receive register (DDCDRR)
0 = No data received
TXIF — DDC Transmit Interrupt Flag
This flag is set when data in the data transmit register (DDCDTR) is
downloaded to the output circuit, and that new data can be written to
the DDCDTR. TXIF generates an interrupt request to CPU if the DIEN
bit in DDCCR is also set. This bit is cleared by writing "0" to it or when
the DEN = 0.
1 = Data transfer completed
0 = Data transfer in progress
MATCH — DDC Address Match
This flag is set when the received data in the data receive register
(DDCDRR) is a calling address which matches with the address or its
extended addresses (EXTAD=1) specified in the DDCADR register.
1 = Received address matches DDCADR
0 = Received address does not match
Data Sheet
244
DDC12AB Interface
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor