MC68HC908LD64 Datasheet, PDF (160/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module (TIM)
11.7.2 Stop Mode
The TIM is inactive after the execution of a STOP instruction. The STOP
instruction does not affect register conditions or the state of the TIM
counter. TIM operation resumes when the MCU exit stop mode after an
external interrupt.
11.8 TIM During Break Interrupts
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the break flag control register (BFCR) enables software to clear status
bits during the break state. (See 23.6.4 SIM Break Flag Control
Register.)
To allow software to clear status bits during a break interrupt, write a
logic one to the BCFE bit. If a status bit is cleared during the break state,
it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic zero to the
BCFE bit. With BCFE at logic zero (its default state), software can read
and write I/O registers during the break state without affecting status
bits. Some status bits have a two-step read/write clearing procedure. If
software does the first step on such a bit before the break, the bit cannot
change during the break state as long as BCFE is at logic zero. After the
break, doing the second step clears the status bit.
11.9 I/O Signals
The TIM channel I/O pin is CLAMP/TCH0. The pin is shared with sync
processor CLAMP output signal.
TCH0 pin is programmable independently as an input capture pin or an
output compare pin. It also can be configured as a buffered output
compare or buffered PWM pin.
Data Sheet
160
Timer Interface Module (TIM)
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor