MC68HC908LD64 Datasheet, PDF (114/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
9.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
9.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
9.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
9.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
9.8.1 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . 134
9.8.2 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . 135
9.8.3 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . 136
9.2 Introduction
This section describes the system integration module, which supports up
to 16 external and/or internal interrupts. Together with the CPU, the SIM
controls all MCU activities. A block diagram of the SIM is shown in
Figure 9-1. Figure 9-2 shows a summary of the SIM I/O registers. The
SIM is a system state controller that coordinates CPU and exception
timing. The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and COP
timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
Data Sheet
114
System Integration Module (SIM)
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor