MC68HC908LD64 Datasheet, PDF (258/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Sync Processor
ATPOL
X
0
0
1
1
Table 17-3. Sync Output Polarity
SOUT
1
0
0
0
0
VINVO
or
HINVO
X
0
1
0
1
Sync Outputs:
VOUT/HOUT
Free-running video mode output
Same polarity as sync input
Inverted polarity of sync input
Negative polarity sync output
Positive polarity sync output
When the SOUT bit is set, the HOUT output is a free-running pulse. Both
HOUT and VOUT outputs are negative polarity, with frequencies
selected by the H & V Sync Output Control Register (HVOCR).
17.5.4 Clamp Pulse Output
When the ELS0B and ELS0A bits in the TSC0 register are logic 0 (see
Table 11-3), a clamp signal is output on the CLAMP pin. This clamp
pulse is triggered either on the leading edge or the trailing edge of
HSYNC, controlled by BPOR bit, with the polarity controlled by the
COINV bit. See Figure 17-3 . Clamp Pulse Output Timing.
HSYNC
(HPOL = 1)
CLAMP
(BPOR = 0)
Pulse width = 0.33~2.1µs
CLAMP
(BPOR = 1)
Pulse width = 0.33~2.1µs
HSYNC
(HPOL = 0)
CLAMP
(BPOR = 0)
Pulse width = 0.33~2.1µs
CLAMP
(BPOR = 1)
Pulse width = 0.33~2.1µs
Figure 17-3. Clamp Pulse Output Timing
Data Sheet
258
Sync Processor
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor