MC68HC908LD64 Datasheet, PDF (246/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

DDC12AB Interface
RXBF — DDC Receive Buffer Full
This flag indicates the status of the data receive register (DDCDRR).
When the CPU reads the data from the DDCDRR, the RXBF flag will
be cleared. RXBF is set when DDCDRR is full by a transfer of data
from the input circuit to the DDCDRR. Reset clears this bit.
1 = Data receive register full
0 = Data receive register empty
16.6.6 DDC Data Transmit Register (DDCDTR)
Address: $001A
Bit 7
6
5
4
3
2
1
Read:
DTD7
Write:
DTD6
DTD5
DTD4
DTD3
DTD2
DTD1
Reset: 1
1
1
1
1
1
1
Figure 16-7. DDC Data Transmit Register (DDCDTR)
Bit 0
DTD0
1
When the DDC module is enabled, DEN = 1, data written into this
register depends on whether module is in master or slave mode.
In slave mode, the data in DDCDTR will be transferred to the output
circuit when:
• the module detects a matched calling address (MATCH = 1), with
the calling master requesting data (SRW = 1); or
• the previous data in the output circuit has be transmitted and the
receiving master returns an acknowledge bit, indicated by a
received acknowledge bit (RXAK = 0).
If the calling master does not return an acknowledge bit (RXAK = 1), the
module will release the SDA line for master to generate a "stop" or
"repeated start" condition. The data in the DDCDTR will not be
transferred to the output circuit until the next calling from a master. The
transmit buffer empty flag remains cleared (TXBE = 0).
In master mode, the data in DDCDTR will be transferred to the output
circuit when:
Data Sheet
246
DDC12AB Interface
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor