MC68HC908LD64 Datasheet, PDF (150/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module (TIM)
11.2 Introduction
This section describes the timer interface module (TIM2, Version B). The
TIM is a two-channel timer that provides a timing reference with input
capture, output compare, and pulse-width-modulation functions.
Figure 11-1 is a block diagram of the TIM.
11.3 Features
Features of the TIM include the following:
• Two input capture/output compare channels
– Rising-edge, falling-edge, or any-edge input capture trigger
– Set, clear, or toggle output compare action
• Buffered and unbuffered pulse width modulation (PWM) signal
generation
• Programmable TIM clock input
– Seven-frequency internal bus clock prescaler selection
• Free-running or modulo up-count operation
• Toggle any channel pin on overflow
• TIM counter stop and reset bits
NOTE:
TCH1 (timer channel 1) is not bonded to an external pin on this MCU.
Therefore, any references to the timer TCH1 pin in the following text
should be interpreted as not available — but the internal status and
control registers are still available.
11.4 Pin Name Conventions
The TIM shares the TCH0 pin with the sync processor CLAMP output.
Table 11-1. Pin Name Conventions
TIM Generic Pin Name:
Full TIM Pin Name:
Pin Selected for TCH0 By:
TCH0
CLAMP/TCH0
ELS0B:ELS0A
Data Sheet
150
Timer Interface Module (TIM)
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor