MC68HC908LD64 Datasheet, PDF (140/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Monitor ROM (MON)
10.4.1 Entering Monitor Mode
Table 10-1 shows the pin conditions for entering monitor mode. As
specified in the table, monitor mode may be entered after a power-on
reset (POR) and will allow communication at 9600 baud provided one of
the following sets of conditions is met:
1. If monitor entry is by high voltage on IRQ (IRQ = V_TST)
– The external clock is 4.9152 MHz with PTC3 low or
9.8304 MHz with PTC3 high
2. If monitor entry is by blank reset vector ($FFFE and $FFFF both
contain $FF; erased state):
– The external clock is 9.8304 MHz
NOTE:
Holding the PTC3 pin low when entering monitor mode by a high voltage
causes a bypass of a divide-by-two stage at the oscillator. The OSCOUT
frequency is equal to the OSCXCLK frequency, and the OSC1 input
directly generates internal bus clocks. In this case, the OSC1 signal
must have a 50% duty cycle at maximum bus frequency.
NOTE:
If the reset vector is blank and monitor mode is entered, the chip will see
an additional reset cycle after the initial POR reset. Once the part has
been programmed, the traditional method of applying a high voltage,
V_TST, to IRQ must be used to enter monitor mode.
Enter monitor mode with the pin configuration shown in Table 10-1 after
a reset. The rising edge of reset latches monitor mode. Once monitor
mode is latched, the values on the specified pins can change.
Once out of reset, the MCU monitor mode firmware then sends a break
signal (10 consecutive logic zeros) to the host computer, indicating that
it is ready to receive a command. The break signal also provides a timing
reference to allow the host to determine the necessary baud rate.
Data Sheet
140
Monitor ROM (MON)
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor