MC68HC908LD64 Datasheet, PDF (112/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
8.8.2 Stop Mode
When the STOP instruction executes, the SIM drives the SIMOSCEN
signal low, disabling the CGM and holding low all CGM outputs
(OSCXCLK, DCLK1, and CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK,
driving DCLK1, the PLL automatically clears the BCS bit in the PLL
control register (PCTL), thereby selecting the crystal clock, OSCXCLK,
as the source of DCLK1. When the MCU recovers from STOP, the
crystal clock drives DCLK1 and BCS remains clear.
8.9 CGM During Break Interrupts
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. See Section 9. System Integration
Module (SIM).
To allow software to clear status bits during a break interrupt, a 1 should
be written to the BCFE bit. If a status bit is cleared during the break state,
it remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a 0 to the BCFE bit.
With BCFE at 0 (its default state), software can read and write the PLL
control register during the break state without affecting the PLLF bit.
Data Sheet
112
Clock Generator Module (CGM)
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor