MC68HC908LD64 Datasheet, PDF (47/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Memory Map
Input/Output (I/O) Section
Addr.
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
Register Name
Bit 7
TIM Channel 1 ^Read: _Bit15
Register High Write:
(TCH1H) _Reset:
TIM Channel 1 ^Read: _Bit7
Register Low Write:
(TCH1L) _Reset:
DDC Master Control ^Read: _ALIF
Register Write:
(DDCMCR) _{Reset: 0}
Read:
DDC Address Register
(DDCADR)
Write:
Reset:
DAD7
1
Read:
DDC Control Register
(DDCCR)
Write:
DEN
Reset: 0
Read: RXIF
DDC Status Register
(DDCSR)
Write:
0
Reset: 0
DDC Data Transmit ^Read:
Register Write:
(DDCDTR) _Reset:
DTD7
1
DDC Data Receive Read:
Register
(DDCDRR)
Write:
Reset:
DRD7
0
Read:
DDC2 Address Register
(DDC2ADR)
Write:
Reset:
D2AD7
0
Read:
Unimplemented Write:
Reset:
6
Bit14
Bit6
NAKIF
0
DAD6
0
DIEN
0
TXIF
0
0
DTD6
1
DRD6
0
D2AD6
0
5
4
3
2
1
Bit 0
Bit13 Bit12 Bit11 Bit10
Bit9
Bit8
Indeterminate after reset
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Indeterminate after reset
BB
MAST MRW BR2
BR1
BR0
0
0
0
0
0
0
DAD5 DAD4 DAD3 DAD2 DAD1 EXTAD
1
0
0
0
0
0
0
0
0
TXAK SCLIEN DDC1EN
0
0
MATCH SRW
0
0
0
RXAK
1
0
SCLIF
0
0
0
TXBE
1
0
RXBF
0
DTD5 DTD4 DTD3 DTD2 DTD1 DTD0
1
DRD5
1
DRD4
1
DRD3
1
DRD2
1
DRD1
1
DRD0
0
0
0
0
0
0
0
D2AD5 D2AD4 D2AD3 D2AD2 D2AD1
0
0
0
0
0
0
U = Unaffected
X = Indeterminate
= Unimplemented
R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 15)
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
Memory Map
Data Sheet
47