MC68HC908LD64 Datasheet, PDF (163/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module (TIM)
I/O Registers
Table 11-2. Prescaler Selection
PS2 PS1 PS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
TIM Clock Source
Internal Bus Clock ÷ 1
Internal Bus Clock ÷ 2
Internal Bus Clock ÷ 4
Internal Bus Clock ÷ 8
Internal Bus Clock ÷ 16
Internal Bus Clock ÷ 32
Internal Bus Clock ÷ 64
Not available
11.10.2 TIM Counter Registers (TCNTH:TCNTL)
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers.
Address: $000C TCNTH
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10
Bit9
Bit8
Write:
Reset: 0
0
0
0
0
0
0
0
Address: $000D TCNTL
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-4. TIM Counter Registers (TCNTH:TCNTL)
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
Timer Interface Module (TIM)
Data Sheet
163