MC68HC908LD64 Datasheet, PDF (24/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

List of Figures
Figure
Title
Page
14-21 USB Embedded Device Endpoint 1/2 Data Registers
(DE1D0–DE1D7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
MMIIC I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . 223
Multi-Master IIC Address Register (MMADR). . . . . . . . . . . . . 224
Multi-Master IIC Control Register (MMCR). . . . . . . . . . . . . . . 225
Multi-Master IIC Master Control Register (MIMCR) . . . . . . . . 226
Multi-Master IIC Status Register (MMSR) . . . . . . . . . . . . . . . 228
Multi-Master IIC Data Transmit Register (MMDTR) . . . . . . . . 230
Multi-Master IIC Data Receive Register (MMDRR) . . . . . . . . 231
Data Transfer Sequences for Master/Slave
Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 233
16-1
16-2
16-3
16-4
16-5
16-6
16-7
16-8
16-9
DDC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 237
DDC Address Register (DDCADR). . . . . . . . . . . . . . . . . . . . . 238
DDC2 Address Register (DDC2ADR). . . . . . . . . . . . . . . . . . . 239
DDC Control Register (DDCCR). . . . . . . . . . . . . . . . . . . . . . . 240
DDC Master Control Register (DDCMCR) . . . . . . . . . . . . . . . 241
DDC Status Register (DDCSR) . . . . . . . . . . . . . . . . . . . . . . .244
DDC Data Transmit Register (DDCDTR) . . . . . . . . . . . . . . . . 246
DDC Data Receive Register (DDCDRR) . . . . . . . . . . . . . . . . 247
Data Transfer Sequences for Master/Slave
Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 249
17-1 Sync Processor I/O Register Summary . . . . . . . . . . . . . . . . . 254
17-2 Sync Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . .255
17-3 Clamp Pulse Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 258
17-4 Sync Processor Control & Status Register (SPCSR) . . . . . . . 259
17-5 Sync Processor Input/Output Control Register (SPIOCR) . . . 261
17-6 Vertical Frequency High Register . . . . . . . . . . . . . . . . . . . . . . 263
17-7 Vertical Frequency Low Register . . . . . . . . . . . . . . . . . . . . . . 263
17-8 Hsync Frequency High Register . . . . . . . . . . . . . . . . . . . . . . . 265
17-9 Hsync Frequency Low Register . . . . . . . . . . . . . . . . . . . . . . .265
17-10 Sync Processor Control Register 1 (SPCR1) . . . . . . . . . . . . . 267
17-11 H&V Sync Output Control Register (HVOCR) . . . . . . . . . . . . 268
Data Sheet
24
List of Figures
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor