MC68HC908LD64 Datasheet, PDF (269/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Sync Processor
System Operation
DCLKPH[1:0] — DCLK Output Phase Adjustment
These two bits are programmed to adjust the DCLK output phase.
Each increment adds approximately 2 to 3ns delay to the DCLK
output.
HVOCR[1:0] — Free Running Video Mode Select Bits
These two bits together with MUL[7:4] and VRS[7:4] in CGM’s PLL
programming register determine the frequencies of the internal
generated free-running signals for output to HOUT, VOUT, DE, and
DCLK pins, when the SOUT bit is set in the sync processor I/O control
register. These two bits determine the prescaler of PLL reference
clock in the CGM module. When HVOCR[1:0]=11, the prescaler is 2;
for other values, the prescaler is 3. Reset clears these bits, setting a
default horizontal frequency of 31.25kHz and a vertical frequency of
60Hz, a video mode of 640×480. (See Section 8. Clock Generator
Module (CGM).)
Table 17-9. Free-Running HSOUT, VSOUT, DE, and DCLK Settings
HVOCR[1:0] MUL[7:4]
00
3
01
5
10
8
11
9
VRS[7:4]
3
3
6
9
HOUT
Frequency
31.45 kHz
37.87 kHz
48.37 kHz
64.32 kHz
VOUT
Frequency
59.91 Hz
60.31 Hz
60.31 Hz
60.00 Hz
DCLK
Frequency
24 MHz
40 MHz
64 MHz
108 MHz
DE Video Mode
VGA 640 × 480
SVGA 800 × 600
XGA 1024 × 768
SXGA 1280 × 1024
17.7 System Operation
This Sync Processor is designed to assist in determining the video mode
of incoming HSYNC and VSYNC of various frequencies and polarities,
and DPMS modes. In the DPMS standard, a no sync pulses definition
can be detected when the value of the Hsync Frequency Register (the
number of Hsync pulses) is less than one or when the VOF bit is set.
Since the Hsync Frequency Register is updated repeatedly in every
32.768ms, and a valid Vsync must have a frequency greater than
40.7Hz, a valid Vsync pulse will arrive within the 32.768ms window.
Therefore, the user should read the Hsync Frequency Register every
32.768ms to determine the presence of Hsync and/or Vsync pulses.
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
Sync Processor
Data Sheet
269