MC68HC908LD64 Datasheet, PDF (119/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
Reset and System Initialization
OSCOUT
RST
IAB PC
VECT H VECT L
Figure 9-4. External Reset Timing
9.4.2 Active Resets from Internal Sources
SIM module in HC08 has the capability to drive the RST pin low when
internal reset events occur.
All internal reset sources actively pull the RST pin low for 32 OSCXCLK
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles (see Figure 9-
5. Internal Reset Timing). An internal reset can be caused by an illegal
address, illegal opcode, COP timeout, or POR (see Figure 9-6. Sources
of Internal Reset). Note that for POR resets, the SIM cycles through
4096 OSCXCLK cycles during which the SIM forces the RST pin low.
The internal reset signal then follows the sequence from the falling edge
of RST shown in Figure 9-5.
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
IRST
RST
OSCXCLK
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
IAB
VECTOR HIGH
Figure 9-5. Internal Reset Timing
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
LVI
INTERNAL RESET
Figure 9-6. Sources of Internal Reset
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
System Integration Module (SIM)
Data Sheet
119