MC68HC908LD64 Datasheet, PDF (279/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

On-Screen Display (OSD)
OSD Module I/O Registers
DENDIF — OSD Display End Interrupt Flag
This bit is set when the OSD has finished the row15 display; it is
cleared by writing a logic 0 to it. The DENDIF bit is designed for user
program to update the OSD RAM while not displaying OSD. Reset
clears this bit.
1 = OSD has finished the row15 display
0 = No effect
18.7.3 OSD Data Registers (OSDDRH:OSDDRL)
Address: $0063
Bit 7
6
5
4
3
2
1
Read:
OSDD15 OSDD14 OSDD13 OSDD12 OSDD11 OSDD10 OSDD9
Write:
Reset:
Unaffected by reset
Figure 18-7. OSD Data Register High (OSDDRH)
0
OSDD8
Address: $0062
Bit 7
6
5
4
3
2
1
Read:
OSDD7 OSDD6 OSDD5 OSDD4 OSDD3 OSDD2 OSDD1
Write:
Reset:
Unaffected by reset
Figure 18-8. OSD Data Register Low (OSDDRL)
0
OSDD0
OSDD[15:0] — OSD RAM 16-Bit Data Buffer
While OSD circuitry is displaying data from the display RAM, update
the display RAM (location specified by the row and column address
registers, OSDRAR and OSDCAR) by writing data to the high byte
register (OSDDRH) followed by the low byte register (OSDDRL). After
writing to the OSDDRL, the OSD buffer write ready bit (WRDY) will be
cleared. WRDY becomes set again when the OSD circuitry has
transferred the content of the OSD data registers to the display RAM.
Reset has no effect on these bits.
(See 18.6 OSD Screen Memory Map.)
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
On-Screen Display (OSD)
Data Sheet
279