MC68HC908LD64 Datasheet, PDF (248/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

DDC12AB Interface
When the DDCDRR is read by the CPU, the receive buffer full flag is
cleared (RXBF = 0), and the next received data is loaded to the
DDCDRR. Each time when new data is loaded to the DDCDRR, the
RXIF interrupt flag is set, indicating that new data is available in
DDCDRR.
The sequence of events for slave receive and master receive are
illustrated in Figure 16-9.
16.7 Programming Considerations
When the DDC module detects an arbitration loss in master mode, it will
release both SDA and SCL lines immediately. But if there are no further
STOP conditions detected, the module will hang up. Therefore, it is
recommended to have time-out software to recover from such ill
condition. The software can start the time-out counter by looking at the
BB (Bus Busy) flag in the DDCMCR and reset the counter on the
completion of one byte transmission. If a time-out occur, software can
clear the DEN bit (disable DDC module) to release the bus, and hence
clearing the BB flag. This is the only way to clear the BB flag by software
if the module hangs up due to a no STOP condition received. The DDC
can resume operation again by setting the DEN bit.
Data Sheet
248
DDC12AB Interface
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor