MC68HC908LD64 Datasheet, PDF (239/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

DDC12AB Interface
DDC Registers
EXTAD — DDC Expanded Address
This bit is set to expand the address of the DDC in slave mode. When
set, the DDC will acknowledge the general call address $00 and the
matched 4-bit address, DAD[7:4]. Reset clears this bit.
For example, when DDCADR is configured as:
DAD7
1
DAD6
1
DAD5
0
DAD4
1
DAD3
X
DAD2
X
DAD1
X
EXTAD
1
The DDC module will respond to the calling address:
Bit 7
6
5
4
3
2
Bit 1
1
1
0
1
X
X
X
or the general calling address:
0
0
0
0
0
0
0
where X = don’t care; bit 0 of the calling address is the MRW bit from
the calling master.
1 = DDC responds to address $00 and $DAD[7:4]
0 = DDC responds to address $DAD[7:1]
16.6.2 DDC2 Address Register (DDC2ADR)
Address: $001C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
D2AD7 D2AD6 D2AD5 D2AD4 D2AD3 D2AD2 D2AD1
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 16-3. DDC2 Address Register (DDC2ADR)
D2AD[7:1] — DDC2 Address
These seven bits represent the second slave address for the DDC2BI
protocol. D2AD[7:1] should be set to the same value as DAD[7:1] in
DDCADR if user application do not use DDC2BI. Reset clears all bits
this register.
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
DDC12AB Interface
Data Sheet
239