MC68HC908LD64 Datasheet, PDF (212/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Universal Serial Bus Module (USB)
RXD0FR — Embedded Device Endpoint 0 Receive Flag Reset
Writing a logic 1 to this write-only bit will clear the RXD0F bit if it is set.
Reset clears this bit.
1 = Write 1 to clear RXD0F bit
0 = No effect
14.7.3 USB Embedded Device Interrupt Register 1 (DIR1)
Address: $004A
Bit 7
6
5
4
3
2
1
Bit 0
Read: TXD1F
0
0
0
0
0
0
TXD1IE
Write:
TXD1FR
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-15. USB Embedded Device Interrupt Register 1 (DIR1)
TXD1F — Embedded Device Endpoint 1/2 Data Transmit Flag
This read-only bit is shared by endpoint 1 and endpoint 2 of the
embedded device. It is set after the data stored in the shared
endpoint 1/2 transmit buffer of the embedded device have been sent
and an ACK handshake packet received from the host. Once the next
set of data is ready in the transmit buffers, software must clear this
flag by writing a logic 1 to the TXD1FR bit. To enable the next data
packet transmission, TX1E must also be set. If TXD1F bit is not
cleared, a NAK handshake will be returned in the next IN transaction.
TXD1F generates an interrupt request to the CPU if the TXD1IE bit is
also set. Writing to TXD1F has no effect. Reset clears this bit.
1 = Transmit on endpoint 1 or endpoint 2 of the embedded device
has occurred
0 = Transmit on endpoint 1 or endpoint 2 of the embedded device
has not occurred
TXD1IE — Embedded Device Endpoint 1/2 Transmit Interrupt Enable
This read/write bit enables the TXD1F bit to generate CPU interrupt
request when set. Reset clears the TXD1IE bit.
1 = TXD1F CPU interrupt requests enabled
0 = TXD1F CPU interrupt requests disabled
Data Sheet
212
Universal Serial Bus Module (USB)
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor