MC68HC908LD64 Datasheet, PDF (180/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
13.4.1 ADC Port I/O Pins
PTC5/ADC5–PTC0/ADC0 are general-purpose I/O pins that are shared
with the ADC channels. The channel select bits, ADCH[4:0], in the ADC
status and control register define which ADC channel/port pin will be
used as the input signal. The ADC overrides the port I/O logic by forcing
that pin as input to the ADC. The remaining ADC channels/port pins are
controlled by the port I/O logic and can be used as general-purpose I/O.
Writes to the port register or DDR will not have any affect on the port pin
that is selected by the ADC. Read of a port pin which is in use by the
ADC will return a logic 0 if the corresponding DDR bit is at logic 0. If the
DDR bit is at logic 1, the value in the port data latch is read.
13.4.2 Voltage Conversion
NOTE:
When the input voltage to the ADC equals to VRH, the ADC converts the
signal to $FF (full scale). If the input voltage equals to VRL, the ADC
converts it to $00. Input voltages between VRH and VRL is a straight-line
linear conversion. All other input voltages will result in $FF if greater than
VRH and $00 if less than VRL.
Input voltage should not exceed the analog supply voltages.
13.4.3 Conversion Time
Sixteen ADC internal clocks are required to perform one conversion. The
ADC starts a conversion on the first rising edge of the ADC internal clock
immediately following a write to the ADSCR. If the ADC internal clock is
selected to run at 1MHz, then one conversion will take 16µs to complete.
With a 1MHz ADC internal clock the maximum sample rate is 62.5kHz.
Conversion time = ^{16 to17 ADC cycles}
ADC frequency
Number of bus cycles = conversion time × bus frequency
Data Sheet
180
Analog-to-Digital Converter (ADC)
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor