MC68HC908LD64 Datasheet, PDF (225/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Multi-Master IIC Interface (MMIIC)
Multi-Master IIC Registers
15.5.2 Multi-Master IIC Control Register (MMCR)
Address: $006C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
MMEN MMIEN
MMTXAK
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 15-3. Multi-Master IIC Control Register (MMCR)
MMEN — Multi-Master IIC Enable
This bit is set to enable the Multi-master IIC module. When
MMEN = 0, module is disabled and all flags will restore to its power-
on default states. Reset clears this bit.
1 = MMIIC module enabled
0 = MMIIC module disabled
MMIEN — Multi-Master IIC Interrupt Enable
When this bit is set, the MMTXIF, MMRXIF, MMALIF, and MMNAKIF
flags are enabled to generate an interrupt request to the CPU. When
MMIEN is cleared, the these flags are prevented from generating an
interrupt request. Reset clears this bit.
1 = MMTXIF, MMRXIF, MMALIF, and/or MMNAKIF bit set will
generate interrupt request to CPU
0 = MMTXIF, MMRXIF, MMALIF, and/or MMNAKIF bit set will not
generate interrupt request to CPU
MMTXAK — Transmit Acknowledge Enable
This bit is set to disable the MMIIC from sending out an acknowledge
signal to the bus at the 9th clock bit after receiving 8 data bits. When
MMTXAK is cleared, an acknowledge signal will be sent at the 9th
clock bit. Reset clears this bit.
1 = MMIIC does not send acknowledge signals at 9th clock bit
0 = MMIIC sends acknowledge signal at 9th clock bit
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
Multi-Master IIC Interface (MMIIC)
Data Sheet
225