MC68HC908LD64 Datasheet, PDF (121/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
Reset and System Initialization
9.4.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
SIM reset status register (SRSR). The SIM actively pulls down the RST
pin for all internal reset sources.
To prevent a COP module timeout, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and bits 12 through 5
of the SIM counter. The SIM counter output, which occurs at least every
2¹² – 2⁴ OSCXCLK cycles, drives the COP counter. The COP should be
serviced as soon as possible out of reset to guarantee the maximum
amount of time before the first timeout.
The COP module is disabled if the RST pin or the IRQ is held at V_TST
while the MCU is in monitor mode. The COP module can be disabled
only through combinational logic conditioned with the high voltage signal
on the RST pin or the IRQ pin. This prevents the COP from becoming
disabled as a result of external noise. During a break state, V_TST on the
RST pin disables the COP module.
9.4.2.3 Low-Voltage Inhibit Reset
The low-voltage inhibit circuit performs an internal reset when the V_DD
voltage falls to the LVI trip voltage V_TRIPF. The external reset pin (RST)
is held low while the SIM counter counts out 4096 OSCXCLK cycles.
Sixty-four OSCXCLK cycles later, the CPU and memories are released
from reset to allow the reset vector sequence to occur.
9.4.2.4 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
If the stop enable bit, STOP, in the configure register (CONFIG) is logic
zero, the SIM treats the STOP instruction as an illegal opcode and
causes an illegal opcode reset. The SIM actively pulls down the RST pin
for all internal reset sources.
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
System Integration Module (SIM)
Data Sheet
121