MC68HC908LD64 Datasheet, PDF (298/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output (I/O) Ports
19.3.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is
an input or an output. Writing a logic 1 to a DDRA bit enables the output
buffer for the corresponding port A pin; a logic 0 disables the output
buffer.
Address: $0004
Bit 7
6
5
4
3
2
1
Read:
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1
Write:
Reset: 0
0
0
0
0
0
0
Figure 19-3. Data Direction Register A (DDRA)
Bit 0
DDRA0
0
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 19-4 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
DDRAx
WRITE PTA ($0000)
PTAx
PTAx
READ PTA ($0000)
Figure 19-4. Port A I/O Circuit
Data Sheet
298
Input/Output (I/O) Ports
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor