MC68HC908LD64 Datasheet, PDF (238/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

DDC12AB Interface
16.5 DDC Protocols
In DDC1 protocol communication, the module is in transmit mode. The
data written to the transmit register is continuously clocked out to the
SDA line by the rising edge of the Vsync input signal. During DDC1
communication, a falling transition on the SCL line can be detected to
generate an interrupt to the CPU for mode switching.
In DDC2AB protocol communication, the module can be either in
transmit mode or in receive mode, controlled by the calling master.
In DDC2 protocol communication, the module will act as a standard IIC
module, able to act as a master or a slave device.
16.6 DDC Registers
Seven registers are associated with the DDC module, they are outlined
in the following sections.
16.6.1 DDC Address Register (DDCADR)
Address: $0017
Bit 7
6
5
4
3
2
1
Read:
DAD7
Write:
DAD6
DAD5
DAD4
DAD3
DAD2
DAD1
Reset: 1
0
1
0
0
0
0
Figure 16-2. DDC Address Register (DDCADR)
Bit 0
EXTAD
0
DAD[7:1] — DDC Address
These seven bits can be the DDC2 interface’s own specific slave
address in slave mode or the calling address when in master mode.
Software must update it as the calling address while entering the
master mode and restore its own slave address after the master mode
is relinquished. Reset sets a default value of $A0.
Data Sheet
238
DDC12AB Interface
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor