MC68HC908LD64 Datasheet, PDF (108/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
XLD — Crystal Loss Detect Bit
When the VCO output, CGMVCLK, is driving DCLK1, this read/write
bit indicates whether the crystal reference frequency is active or not.
To check the status of the crystal reference, the following procedure
should be followed:
1. Write a 1 to XLD.
2. Wait 4 × N cycles. (N is the VCO frequency multiplier, MUL[7:4].)
3. Read XLD.
1 = Crystal reference is not active
0 = Crystal reference is active
The crystal loss detect function works only when the BCS bit is set,
selecting CGMVCLK to drive DCLK1. When BCS is clear, XLD always
reads as 0.
Bits [3:0] — Reserved for test
These bits enable test functions not available in user mode. To ensure
software portability from development systems to user applications,
software should write zeros to Bits [3:0] whenever writing to PBWC.
8.6.3 PLL Programming Register (PPG)
The PLL programming register contains the programming information for
the modulo feedback divider and the programming information for the
hardware configuration of the VCO.
Address: $003A
Bit 7
6
5
4
3
2
1
Read:
MUL7
Write:
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
Reset: 0
1
1
0
0
1
1
Figure 8-5. PLL Programming Register (PPG)
Bit 0
VRS4
0
Data Sheet
108
Clock Generator Module (CGM)
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor