MC68HC908LD64 Datasheet, PDF (103/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
CGM I/O Signals
8.4.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an
external crystal. The OSC1 pin is the input to the amplifier and the OSC2
pin is the output. The SIMOSCEN signal from the system integration
module (SIM) enables the crystal oscillator circuit.
The OSCXCLK signal is the output of the crystal oscillator circuit and
runs at a rate equal to the crystal frequency. OSCXCLK is then buffered
to produce OSCRCLK, the PLL reference clock. (See Section 7.
Oscillator (OSC).)
8.5 CGM I/O Signals
The following paragraphs describe the CGM I/O signals.
8.5.1 External Filter Capacitor Pin (CGMXFC)
NOTE:
The CGMXFC pin is required by the loop filter to filter out phase
corrections. A small external capacitor (C_F) is connected to this pin.
To prevent noise problems, C_F should be placed as close to the
CGMXFC pin as possible, with minimum routing distances and no
routing of other signals across the C_F connection.
8.5.2 PLL Analog Power Pin (VDDA)
VDDA is the power pin used by the analog portions of the PLL. The pin
should be connected to the same voltage potential as the VDD pin.
8.5.3 PLL Analog Ground Pin (VSSA)
VSSA is the ground pin used by the analog portions of the PLL. The pin
should be connected to the same voltage potential as the VSS pin.
NOTE: Route VDDA and VSSA carefully for maximum noise immunity and
place bypass capacitors as close as possible to the package.
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
Clock Generator Module (CGM)
Data Sheet
103