MC68HC908LD64 Datasheet, PDF (109/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
CGM I/O Registers
MUL[7:4] — Multiplier Select Bits
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier, N. A value of $0 in the multiplier select
bits configures the modulo feedback divider the same as a value of
$1. Reset initializes these bits to $6 to give a default multiply value
of 6.
Table 8-2. VCO Frequency Multiplier (N) Selection
MUL7:MUL6:MUL5:MUL4
0000
0001
0010
0011
VCO Frequency Multiplier (N)
1
1
2
3
1101
13
1110
14
1111
15
NOTE: The multiplier select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1).
VRS[7:4] — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear
multiplier L, which controls the hardware center-of-range frequency
f_VRS. VRS[7:4] cannot be written when the PLLON bit in the PLL
control register (PCTL) is set. A value of $0 in the VCO range select
bits disables the PLL and clears the BCS bit in the PCTL. Reset
initializes the bits to $6 to give a default range multiply value of 6.
NOTE:
The VCO range select bits have built-in protection that prevents them
from being written when the PLL is on (PLLON = 1) and prevents
selection of the VCO clock as the source of the base clock (BCS = 1) if
the VCO range select bits are all clear.
The VCO range select bits must be programmed correctly. Incorrect
programming may result in failure of the PLL to achieve lock.
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
Clock Generator Module (CGM)
Data Sheet
109