MC68HC908LD64 Datasheet, PDF (106/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
PLLON — PLL On Bit
This read/write bit activates the PLL and enables the VCO clock,
CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the
base clock, DCLK1 (BCS = 1). Reset sets this bit so that the loop can
stabilize as the MCU is powering up.
1 = PLL on
0 = PLL off
BCS — Base Clock Select Bit
This read/write bit selects either the crystal oscillator output,
OSCXCLK, or the VCO clock, CGMVCLK, as the source of the CGM
output, DCLK1. BCS cannot be set while the PLLON bit is clear. After
toggling BCS, it may take up to three OSCXCLK and three CGMVCLK
cycles to complete the transition from one source clock to the other.
During the transition, DCLK1 is held in stasis. Reset and the STOP
instruction clear the BCS bit.
1 = DCLK1 driven by CGMVCLK
0 = DCLK1 driven by OSCXCLK
NOTE:
PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base
clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS
is set, and BCS cannot be set when PLLON is clear. If the PLL is off
(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control
register.
8.6.2 PLL Bandwidth Control Register (PBWC)
The PLL bandwidth control register does the following:
• Selects automatic or manual (software-controlled) bandwidth
control mode
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
• In manual operation, forces the PLL into acquisition or tracking
mode
Data Sheet
106
Clock Generator Module (CGM)
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor