MC68HC908LD64 Datasheet, PDF (229/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Multi-Master IIC Interface (MMIIC)
Multi-Master IIC Registers
MMTXIF — Multi-Master Transmit Interrupt Flag
This flag is set when data in the data transmit register (MMDTR) is
downloaded to the output circuit, and that new data can be written to
the MMDTR. MMTXIF generates an interrupt request to CPU if the
MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it
or when the MMEN = 0.
1 = Data transfer completed
0 = Data transfer in progress
MMATCH — Multi-Master Address Match
This flag is set when the received data in the data receive register
(MMDRR) is an calling address which matches with the address or its
extended addresses (MMEXTAD=1) specified in the MMADR
register.
1 = Received address matches MMADR
0 = Received address does not match
MMSRW — Multi-Master Slave Read/Write
This bit indicates the data direction when the module is in slave mode.
It is updated after the calling address is received from a master
device. MMSRW = 1 when the calling master is reading data from the
module (slave transmit mode). MMSRW = 0 when the master is
writing data to the module (receive mode).
1 = Slave mode transmit
0 = Slave mode receive
MMRXAK — Multi-Master Receive Acknowledge
When this bit is cleared, it indicates an acknowledge signal has been
received after the completion of 8 data bits transmission on the bus.
When MMRXAK is set, it indicates no acknowledge signal has been
detected at the 9th clock; the module will release the SDA line for the
master to generate "stop" or "repeated start" condition. Reset sets this
bit.
1 = No acknowledge signal received at 9th clock bit
0 = Acknowledge signal received at 9th clock bit
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
Multi-Master IIC Interface (MMIIC)
Data Sheet
229