MC68HC908LD64 Datasheet, PDF (231/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Multi-Master IIC Interface (MMIIC)
Multi-Master IIC Registers
If the calling master does not return an acknowledge bit (MMRXAK = 1),
the module will release the SDA line for master to generate a "stop" or
"repeated start" condition. The data in the MMDTR will not be transferred
to the output circuit until the next calling from a master. The transmit
buffer empty flag remains cleared (MMTXBE = 0).
In master mode, the data in MMDTR will be transferred to the output
circuit when:
• the module receives an acknowledge bit (MMRXAK = 0), after
setting master transmit mode (MMRW = 0), and the calling
address has been transmitted; or
• the previous data in the output circuit has be transmitted and the
receiving slave returns an acknowledge bit, indicated by a
received acknowledge bit (MMRXAK = 0).
If the slave does not return an acknowledge bit (MMRXAK = 1), the
master will generate a "stop" or "repeated start" condition. The data in
the MMDTR will not be transferred to the output circuit. The transmit
buffer empty flag remains cleared (MMTXBE = 0).
The sequence of events for slave transmit and master transmit are
illustrated in Figure 15-8.
15.5.6 Multi-Master IIC Data Receive Register (MMDRR)
Address
:
$006F
Bit 7
6
5
4
3
2
1
Bit 0
Read: MMRD7 MMRD6 MMRD5 MMRD4 MMRD3 MMRD2 MMRD1 MMRD0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemente
d
Figure 15-7. Multi-Master IIC Data Receive Register (MMDRR)
When the MMIIC module is enabled, MMEN = 1, data in this read-only
register depends on whether module is in master or slave mode.
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
Multi-Master IIC Interface (MMIIC)
Data Sheet
231