MC68HC908LD64 Datasheet, PDF (249/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

DDC12AB Interface
Programming Considerations
(a) Master Transmit Mode
START
Address 0 ACK
TX Data1
ACK
TX DataN
NAK STOP
TXBE=0
MRW=0
MAST=1
Data1 → DDCDTR
TXBE=1
TXIF=1
Data2 → DDCDTR
TXBE=1
TXIF=1
Data3 → DDCDTR
TXBE=1 NAKIF=1
TXIF=1 MAST=0
DataN+2 → DDCDTR TXBE=0
(b) Master Receive Mode
START
Address 1 ACK
RX Data1
ACK
RX DataN
NAK STOP
RXBF=0
MRW=1
MAST=1
TXBE=0
(dummy data → DDCDTR)
Data1 → DDCDRR
RXIF=1
RXBF=1
DataN → DDCDRR
RXIF=1
RXBF=1
NAKIF=1
MAST=0
(c) Slave Transmit Mode
START
Address 1 ACK
TX Data1
ACK
TX DataN
NAK STOP
TXBE=1
RXBF=0
RXIF=1
RXBF=1
MATCH=1
SRW=1
Data1 → DDCDTR
TXBE=1
TXIF=1
Data2 → DDCDTR
(d) Slave Receive Mode
START
Address 0 ACK
RX Data1
ACK
TXBE=1
TXIF=1
DataN+2 → DDCDTR
NAKIF=1
TXBE=0
RX DataN
NAK STOP
TXBE=0
RXBF=0
RXIF=1
RXBF=1
MATCH=1
SRW=0
Data1 → DDCDRR
RXIF=1
RXBF=1
KEY: shaded data packets indicate a transmit by the MCU’s DDC module
DataN → DDCDRR
RXIF=1
RXBF=1
Figure 16-9. Data Transfer Sequences for Master/Slave Transmit/Receive Modes
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
DDC12AB Interface
Data Sheet
249