MC68HC908LD64 Datasheet, PDF (306/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output (I/O) Ports
19.6 Port D
Port D is an 8-bit special-function port that shares two of its pins with the
multi-master IIC (MMIIC) module, two of its pins with the DDC12AB
module, and four of its pins with the sync processor.
19.6.1 Port D Data Register
The port D data register (PTD) contains a data latch for each of the eight
port D pins.
Address: $0003
Bit 7
6
5
4
3
2
Read:
PTD7
Write:
PTD6
PTD5
PTD4
PTD3
PTD2
Reset:
Unaffected by reset
Alternative Function: IICSDA IICSCL DDCSDA DDCSCL HOUT VOUT
Figure 19-13. Port D Data Register (PTD)
1
PTD1
DE
Bit 0
PTD0
DCLK
PTD[7:0] — Port D Data Bits
These read/write bits are software-programmable. Data direction of
each port D pin is under the control of the corresponding bit in data
direction register D. Reset has no effect on port D data.
IICSDA, IICSCL — Multi-master IIC Data and Clock pins
The PTD7/IICSDA and PTD6/IICSCL pins are multi-master IIC data
and clock pins. When the IICDATE and IICSCLE bits in the port D
control register (PDCR) are clear, the PTD7/IICSDA and
PTD6/IICSCL pins are available for general-purpose I/O.
(See 19.6.3 Port D Options.)
DDCSCL, DDCSDA — DDC12AB Data and Clock pins
The PTD4/DDCSCL and PTD5/DDCSDA pins are DDC12AB clock
and data pins respectively. When the DDCSCLE and DDCDATE bits
in the port D control register (PDCR) are clear, the PTD4/DDCSCL
and PTD5/DDCSDA pins are available for general-purpose I/O. (See
19.6.3 Port D Options.)
Data Sheet
306
Input/Output (I/O) Ports
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor