MC68HC908LD64 Datasheet, PDF (102/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
Addr. Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PLLF
1
1
1
1
$0038
PLL Control Register
(PCTL)
Write:
PLLIE
PLLON BCS
Reset: 0
0
1
0
1
1
1
1
PLL Bandwidth Control ^Read: _AUTO
LOCK
ACQ
XLD
0
0
0
0
$0039
Register Write:
(PBWC) _{Reset: 0}
0
0
0
0
0
0
0
$003A
PLL Programming ^Read:
Register Write:
(PPG) _Reset:
MUL7
0
MUL6
1
MUL5
1
MUL4
0
VRS7
0
VRS6
1
VRS5
1
VRS4
0
H&V Sync Output Control ^Read:
$003F
Register Write:
(HVOCR) _Reset:
DCLKPH1 DCLKPH0 R HVOCR1 HVOCR0
0
0
0
0
= Unimplemented
R = Reserved
NOTES:
1. When AUTO = 0, PLLIE is forced to logic zero and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic zero.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic zero and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Figure 8-2. CGM I/O Register Summary
Table 8-1. Free-Running HSOUT, VSOUT, DE, and DCLK Settings
Register Settings
HVOCR[1:0] MUL[7:4] VRS[7:4]
00
3
3
01
5
3
10
8
6
11
9
9
Output Pin
HOUT
VOUT
DCLK
Frequency Frequency Frequency
31.45kHz 59.91Hz
24 MHz
37.87kHz 60.31Hz
40 MHz
48.37kHz 60.31Hz
64 MHz
64.32kHz 60.00Hz
108 MHz
Video Modes
DE Video Mode
VGA 640 × 480
SVGA 800 × 600
XGA 1024 × 768
SXGA 1280 × 1024
Data Sheet
102
Clock Generator Module (CGM)
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor