MC68HC908LD64 Datasheet, PDF (247/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

DDC12AB Interface
DDC Registers
• the module receives an acknowledge bit (RXAK = 0), after
setting master transmit mode (MRW = 0), and the calling address
has been transmitted; or
• the previous data in the output circuit has be transmitted and the
receiving slave returns an acknowledge bit, indicated by a
received acknowledge bit (RXAK = 0).
If the slave does not return an acknowledge bit (RXAK = 1), the master
will generate a "stop" or "repeated start" condition. The data in the
DDCDTR will not be transferred to the output circuit. The transmit buffer
empty flag remains cleared (TXBE = 0).
The sequence of events for slave transmit and master transmit are
illustrated in Figure 16-9.
16.6.7 DDC Data Receive Register (DDCDRR)
Address: $001B
Bit 7
6
5
4
3
2
1
Read: DRD7 DRD6 DRD5 DRD4 DRD3 DRD2 DRD1
Write:
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 16-8. DDC Data Receive Register (DDCDRR)
Bit 0
DRD0
0
When the DDC module is enabled, DEN = 1, data in this read-only
register depends on whether module is in master or slave mode.
In slave mode, the data in DDCDRR is:
• the calling address from the master when the address match flag
is set (MATCH = 1); or
• the last data received when MATCH = 0.
In master mode, the data in the DDCDRR is:
• the last data received.
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
DDC12AB Interface
Data Sheet
247