MC68HC908LD64 Datasheet, PDF (230/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Multi-Master IIC Interface (MMIIC)
MMTXBE — Multi-Master Transmit Buffer Empty
This flag indicates the status of the data transmit register (MMDTR).
When the CPU writes the data to the MMDTR, the MMTXBE flag will
be cleared. MMTXBE is set when MMDTR is emptied by a transfer of
its data to the output circuit. Reset sets this bit.
1 = Data transmit register empty
0 = Data transmit register full
MMRXBF — Multi-Master Receive Buffer Full
This flag indicates the status of the data receive register (MMDRR).
When the CPU reads the data from the MMDRR, the MMRXBF flag
will be cleared. MMRXBF is set when MMDRR is full by a transfer of
data from the input circuit to the MMDRR. Reset clears this bit.
1 = Data receive register full
0 = Data receive register empty
15.5.5 Multi-Master IIC Data Transmit Register (MMDTR)
Address: $006E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
MMTD7 MMTD6 MMTD5 MMTD4 MMTD3 MMTD2 MMTD1 MMTD0
Write:
Reset: 1
1
1
1
1
1
1
1
Figure 15-6. Multi-Master IIC Data Transmit Register (MMDTR)
When the MMIIC module is enabled, MMEN = 1, data written into this
register depends on whether module is in master or slave mode.
In slave mode, the data in MMDTR will be transferred to the output circuit
when:
• the module detects a matched calling address (MMATCH = 1),
with the calling master requesting data (MMSRW = 1); or
• the previous data in the output circuit has be transmitted and the
receiving master returns an acknowledge bit, indicated by a
received acknowledge bit (MMRXAK = 0).
Data Sheet
230
Multi-Master IIC Interface (MMIIC)
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor