MC68HC908LD64 Datasheet, PDF (254/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Sync Processor
Addr. Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
VSIF
Sync Processor Control
VSIE VEDGE
VPOL
COMP VINVO HINVO
HPOL
$0040
and Status Register Write:
0
(SPCSR)
Reset: 0
0
0
0
0
0
0
0
Read: VOF
0
Vertical Frequency High
0
VF12 VF11 VF10
VF9
VF8
$0041
Register Write:
CPW1 CPW0
(VFHR)
Reset: 0
0
0
0
0
0
0
0
Read: VF7
VF6
VF5
VF4
VF3
VF2
VF1
VF0
Vertical Frequency Low
$0042
Register Write:
(VFLR)
Reset: 0
0
0
0
0
0
0
0
$0043
Read:
Hsync Frequency High
Register Write:
(HFHR)
Reset:
HFH7
0
HFH6
0
HFH5
0
HFH4
0
HFH3
0
HFH2
0
HFH1
0
HFH0
0
Read: HOVER
0
Hsync Frequency Low
$0044
Register Write:
(HFLR)
Reset: 0
0
0
HFL4 HFL3 HFL2 HFL1 HFL0
0
0
0
0
0
0
Read: VSYNCS HSYNCS
$0045
Sync
Processor I/O Control
Register (SPIOCR)
Write:
COINV
R
R
R
BPOR SOUT
Reset: 0
0
0
0
0
Read:
LVSIF
Sync Processor Control
LVSIE
HPS1 HPS0
R
$0046
Register 1 Write:
0
(SPCR1)
Reset: 0
0
0
0
R
ATPOL FSHF
0
0
Read:
H&V Sync Output Control
$003F
Register Write:
(HVOCR)
Reset:
DCLKPH1 DCLKPH0 R HVOCR1 HVOCR0
0
0
0
0
= Unimplemented
R = Reserved
Figure 17-1. Sync Processor I/O Register Summary
Data Sheet
254
Sync Processor
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor