MC68HC908LD64 Datasheet, PDF (261/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Sync Processor
Sync Processor I/O Registers
Table 17-4. ATPOL, VINVO, and HINVO setting
ATPOL
0
0
1
1
VINVO / HINVO
0
1
0
1
Sync Outputs:
VOUT/HOUT
Same polarity as sync input
Inverted polarity of sync input
Negative polarity sync output
Positive polarity sync output
VPOL — Vsync Input Polarity
This bit indicates the polarity of the VSYNC input, or the extracted
Vsync from a composite sync input (COMP=1). Reset clears this bit.
1 = Vsync is positive polarity
0 = Vsync is negative polarity
HPOL — Hsync Input Polarity
This bit indicates the polarity of the HSYNC input. This bit equals the
VPOL bit when the COMP bit is set. Reset clears this bit.
1 = Hsync is positive polarity
0 = Hsync is negative polarity
17.6.2 Sync Processor Input/Output Control Register (SPIOCR)
Address: $0045
Bit 7
6
5
4
3
2
1
Bit 0
Read: VSYNCS HSYNCS
COINV
R
R
R
BPOR SOUT
Write:
Reset: 0
0
0
0
0
= Unimplemented
R = Reserved
Figure 17-5. Sync Processor Input/Output Control Register (SPIOCR)
VSYNCS — VSYNC Input State
This read-only bit reflects the logical state of the VSYNC input.
HSYNCS — HSYNC Input State
This read-only bit reflects the logical state of the HSYNC input.
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
Sync Processor
Data Sheet
261