MC68HC908LD64 Datasheet, PDF (283/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

On-Screen Display (OSD)
OSD Registers
18.8.2 Row Attribute Registers
The 15 row attribute registers are at column 30 of the display rows.
These registers are memory mapped to RAM locations as illustrated in
Figure 18-4.
When OSDMEN=0 (not displaying), CPU has direct access to these
registers by reading/writing the RAM locations. When OSDMEN=1
(displaying), CPU access these registers indirectly by writing to the OSD
data registers, row register and column register.
Each row attribute register affects characters of a display row.
Row 0–14, Column 30:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REN CHS CWS
REN — Row Enable
Set this bit to enable OSD circuitry to display the current row of
characters. This bit should be cleared when display RAM is accessed
directly by the CPU and when the row points to a font that is to be
updated in the FLASH font memory.
1 = Enable display for this row
0 = Disable display for this row
CHS — Character Height
Set this bit to display double height characters for this row.
1 = Display characters as double height for this row
0 = Display characters as normal height for this row
CWS — Character Width
Set this bit to display double width characters for this row.
1 = Display characters as double width for this row
0 = Display characters as normal width for this row
18.8.3 Control, Window, and Pattern Registers
Row-15 registers are for window, pattern, and miscellaneous control of
the entire OSD screen. These registers are NOT memory mapped to
RAM locations. CPU access these registers by writing to the OSD data
registers, row register and column register.
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
On-Screen Display (OSD)
Data Sheet
283