MC68HC908LD64 Datasheet, PDF(346/362 Page) Freescale Semiconductor, Inc – Microcontrollers

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MC68HC908LD64 Datasheet, PDF (346/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

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Electrical Specifications

24.6 DC Electrical Characteristics

Table 24-4. DC Electrical Characteristics

Characteristic(1)

Symbol

Min

Typ(2)

Max

Unit

Output high voltage (ILOAD = â2.0mA)

All output pins

VOH

2.4

â

â

V

Output low voltage (ILOAD = 1.6mA)

All output pins

VOL

â

â

0.4

V

Input high voltage

All ports (except PTD4âPTD7), IRQ, RST, OSC1

For +5V rated pins

VIH

HSYNC, VSYNC, PHSYNC, PVSYNC, PCLK,

IICSDA, IICSCL, DDCSDA, DDCSCL

0.7 Ã VDD

â

2.0

â

VDD

V

5.5

Input low voltage

All ports (except PTD4âPTD7), IRQ, RST, OSC1

For +5V rated pins

VIL

HSYNC, VSYNC, PHSYNC, PVSYNC, PCLK,

IICSDA, IICSCL, DDCSDA, DDCSCL

VSS

â

0.2 Ã VDD

V

VSS

â

0.8

VDD supply current

Run, USB active, PLL on, fOP = 6.0 MHz(3)

Run, USB suspended, PLL off, fOP = 6.0 MHz(3)

Wait, USB active, PLL on, fOP = 6.0 MHz(4)

IDD

Wait, USB suspended, PLL off, fOP = 6.0 MHz(4)

Stop(5) 0Â°C to +85Â°C

â

11

20

mA

â

9

16

mA

â

6

12

mA

â

4

8

mA

â

100

200

ÂµA

I/O ports Hi-Z leakage current

IIL

Input current

All input pins (except below pins)

IIN

HSYNC, VSYNC, PHSYNC, PVSYNC, PCLK

â

â

Â± 10

ÂµA

â

â

â

â

Â±1

Â±2

ÂµA

Capacitance

Ports (as input or output)

POR re-arm voltage(6)

POR rise time ramp rate(7)

Monitor mode entry voltage

Pull-up resistor: KBI0âKBI7, RST, IRQ

Low-voltage inhibit, trip falling voltage

Low-voltage inhibit, trip rising voltage

Low-voltage inhibit reset/recover hysteresis

COUT

CIN

VPOR

RPOR

VTST

RPU

VTRIPF

VTRIPR

VHYS

â

â

0

0.035

VDD + 1.7

30

â

â

â

â

â

â

45

2.45

2.6

150

12

8

pF

100

mV

â

V/ms

6

V

60

kâ¦

V

V

â

mV

Notes:

1. VDD = 3.0 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.

2. Typical values reflect average measurements at midpoint of voltage range, 25 Â°C only.

3. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF

on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all

modules enabled.

4. Wait IDD measured using external square wave clock source (fOSCXCLK = 24MHz); all inputs 0.2 V from rail; no dc loads; less than

100 pF on all outputs. CL = 20 pF on OSC2; USB in suspend mode, 15kâ¦ Â± 5% termination resistors on D+ and Dâ pins; all ports

configured as inputs; OSC2 capacitance linearly affects wait IDD.

5. STOP IDD measured with USB in suspend mode, OSC1 grounded, 1.5kâ¦ Â± 1% pull-up resistor on D+ pin and 15kâ¦ Â± 1% pull-

down resistors on D+ and Dâ pins, no port pins sourcing current.

6. Maximum is highest voltage that POR is guaranteed.

7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD

is reached.

Data Sheet

MC68HC908LD64 â Rev. 3.0

346

Electrical Specifications

Freescale Semiconductor

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