MC68HC908LD64 Datasheet, PDF (169/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module (TIM)
I/O Registers
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of
the TIM channel x registers (TCHxH) inhibits output compares until the
low byte (TCHxL) is written.
Address: $0011 TCH0H
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10
Bit9
Bit8
Write:
Reset:
Indeterminate after reset
Address: $0012 TCH0L
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Write:
Reset:
Indeterminate after reset
Address: $0014 TCH1H
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10
Bit9
Bit8
Write:
Reset:
Indeterminate after reset
Address: $0015 TCH1L
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Write:
Reset:
Indeterminate after reset
Figure 11-8. TIM Channel Registers (TCH0H/L:TCH1H/L)
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
Timer Interface Module (TIM)
Data Sheet
169