MC68HC908LD64 Datasheet, PDF (278/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

On-Screen Display (OSD)
CLKPH[1:0] — Pixel Clock Phase Adjustment
These two bits adjust the pixel clock phase to the OSD module. Thus
the OSDR, OSDG, and OSDB outputs can be in phase with video
signals. Reset clears all these bits.
HALFCLK — Half Frequency of Pixel Clock
This bit is set to divide the incoming pixel clock by two as the OSD
display clock. Reset clears this bit.
1 = OSD module display clock is PCLK divided-by-2
0 = OSD module display clock is PCLK divided-by-1
OSDIEN — OSD Interrupt Enable
This bit enable OSD interrupt when DENDIF in the OSD status
register is set. Reset clear this bit.
1 = DENDIF bit set will generate interrupt request to CPU
0 = DENDIF bit set will not generate interrupt request to CPU
18.7.2 OSD Status Register (OSDSR)
Address: $0061
Bit 7
6
5
4
3
2
1
Read: WRDY
Write:
Reset: 1
= Unimplemented
Figure 18-6. OSD Status Register (OSDSR)
0
DENDIF
0
0
WRDY — OSD Buffer Write Ready
This bit is set when the OSD data registers, $0062 and $0063, are
ready to be loaded with new data. The WRDY is cleared after the CPU
writes to the low byte register, $0062. It becomes set again when the
OSD circuitry has transferred the content of data registers to the
display RAM. Reset sets this bit.
1 = OSD data buffers ready for new data
0 = OSD data buffers busy
Data Sheet
278
On-Screen Display (OSD)
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor