MC68HC908LD64 Datasheet, PDF (118/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
In wait mode, the CPU clocks are inactive. The SIM also produces two
sets of clocks for other modules. Refer to the wait mode subsection of
each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
9.4 Reset and System Initialization
The MCU has the following reset sources:
• Power-on reset module (POR)
• External reset pin (RST)
• Computer operating properly module (COP)
• Low-voltage inhibit (LVI)
• Illegal opcode
• Illegal address
All of these resets produce the vector $FFFE–$FFFF ($FEFE–$FEFF in
monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
An internal reset clears the SIM counter (see 9.5 SIM Counter), but an
external reset does not. Each of the resets sets a corresponding bit in
the SIM reset status register (SRSR) (see 9.8 SIM Registers).
9.4.1 External Pin Reset
Pulling the asynchronous RST pin low halts all processing. The PIN bit
of the SIM reset status register (SRSR) is set as long as RST is held low
for a minimum of 67 OSCXCLK cycles, assuming that the POR was not
the source of the reset (see Table 9-2. PIN Bit Set Timing). Figure 9-4
shows the relative timing.
Table 9-2. PIN Bit Set Timing
Reset Type
POR
All others
Number of Cycles Required to Set PIN
4163 (4096 + 64 + 3)
67 (64 + 3)
Data Sheet
118
System Integration Module (SIM)
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor