MC68HC908LD64 Datasheet, PDF (104/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
8.5.4 Crystal Output Frequency Signal (OSCXCLK)
OSCXCLK is the crystal oscillator output signal. It runs at the full speed
of the crystal (f_XCLK) and is generated directly from the crystal oscillator
circuit. The duty cycle of OSCXCLK is unknown and may depend on the
crystal and other external factors. Also, the frequency and amplitude of
OSCXCLK can be unstable at start-up.
8.5.5 Crystal Reference Frequency Signal (OSCRCLK)
OSCRCLK is the buffered version of OSCXCLK. It runs at the full speed
of the crystal (f_XCLK) and provides the reference for the PLL circuit.
8.5.6 CGM Base Clock Output (DCLK1)
DCLK1 is the clock output of the CGM. This signal goes to the sync
processor, which generates the display clocks. DCLK1 is software
programmable to be either the oscillator output (OSCXCLK) or the VCO
clock (CGMVCLK).
8.5.7 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
8.6 CGM I/O Registers
The following registers control and monitor operation of the CGM:
• PLL control register (PCTL)
• PLL bandwidth control register (PBWC)
• PLL programming register (PPG)
• H & V sync output control register (HVOCR)
Data Sheet
104
Clock Generator Module (CGM)
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor