MC68HC908LD64 Datasheet, PDF (141/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Table 10-1. Monitor Mode Signal Requirements and Options
IRQ
RST
Address
$FFFE/
$FFFF
PTC3
PTC1
PTC0
PTA7⁽¹⁾
DPLUS0
DMINUS0
PTD4
PTD5
X
GND
X
X
X
X
X
X
V_TST
V_DD
X
0
0
1
0
0
or
V_TST
V_TST
V_DD
X
1
0
1
0
0
or
V_TST
V_DD
V_DD
Blank
X
X
X
0
0
or
"$FFFF"
GND
V_DD
V_DD Not Blank
X
X
X
X
X
or
GND
Notes:
1. PTA7 = 0 if serial communication; PTA7 = 1 if parallel communication
2. External clock is derived by a 4.9152/9.8304 MHz crystal or off-chip oscillator
External
Clock⁽²⁾
Bus
Frequency
COP
X
0
Disabled
4.9152
MHz
2.4576
MHz
Disabled
9.8304
MHz
2.4576
MHz
Disabled
9.8304
MHz
2.4576
MHz
Disabled
X
—
Enabled
Baud
Rate
Comment
0
9600
9600
9600
—
No operation until
reset goes high.
Enters monitor mode.
PTC0, PTC1, and PTC3
voltages only required if
IRQ = V_TST;
PTC3 determines
frequency divider.
Exit monitor mode by POR
or by RST low then high
Enters monitor mode.
PTC0, PTC1, and PTC3
voltages only required if
IRQ = V_TST;
PTC3 determines
frequency divider.
Exit monitor mode by POR
or by RST low then high
Enters monitor mode.
External frequency always
divided by 4.
Exit monitor mode by POR
only.
Enters user mode.