MC68HC908LD64 Datasheet, PDF (307/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output (I/O) Ports
Port D
HOUT— Sync Processor HOUT Pulse Output Pin
The PTD3/HOUT pin is the sync processor HOUT pulse output pin.
When the HOUTE bit in the port D control register (PDCR) is clear,
the PTD3/HOUT pin is available for general-purpose I/O. (See 19.6.3
Port D Options.)
VOUT — Sync Processor VOUT Pulse Output Pin
The PTD2/VOUT pin is the sync processor VOUT pulse output pin.
When the VOUTE bit in the port D control register (PDCR) is clear, the
PTD2/VOUT pin is available for general-purpose I/O. (See 19.6.3
Port D Options.)
DE — Sync Processor DE Pulse Output Pin
The PTD1/DE pin is the sync processor DE pulse output pin. When
the DEE bit in the port D control register (PDCR) is clear, the
PTD1/DE pin is available for general-purpose I/O. (See 19.6.3 Port D
Options.)
DCLK — Sync Processor DCLK Pulse Output Pin
The PTD0/DCLK pin is the sync processor DCLK pulse output pin.
When the DCLKE bit in the port D control register (PDCR) is clear, the
PTD0/DCLK pin is available for general-purpose I/O. (See 19.6.3
Port D Options.)
19.6.2 Data Direction Register D
Data direction register D (DDRD) determines whether each port D pin is
an input or an output. Writing a logic 1 to a DDRD bit enables the output
buffer for the corresponding port D pin; a logic 0 disables the output
buffer.
Address: $0007
Bit 7
6
5
4
3
2
1
Read:
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1
Write:
Reset: 0
0
0
0
0
0
0
Figure 19-14. Data Direction Register D (DDRD)
Bit 0
DDRD0
0
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
Input/Output (I/O) Ports
Data Sheet
307