MC68HC908LD64 Datasheet, PDF (262/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Sync Processor
COINV — Clamp Output Invert
This bit is set to invert the clamp pulse output to negative. Reset
clears this bit.
1 = Clamp output is set for negative pulses
0 = Clamp output is set for positive pulses
BPOR — Back Porch
This bit defines the triggering edge of the clamp pulse output relative
to the HSYNC input. Reset clears this bit.
1 = Clamp pulse is generated on the trailing edge of HSYNC
0 = Clamp pulse is generated on the leading edge of HSYNC
SOUT — Sync Output Enable
This bit will select the output signals for the VOUT and HOUT pins and
generate the DE and DCLK signals to the pins. Reset clears this bit.
1 = VOUT, HOUT, DE, and DCLK outputs are internally generated
free-running timing pulses with frequencies determined by
HVCOR[1:0] bits in HVCOR and CGM values.
0 = VOUT and HOUT outputs are processed VSYNC and HSYNC
inputs respectively and DE and DCLK are hold as logic low.
Data Sheet
262
Sync Processor
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor