MC68HC908LD64 Datasheet, PDF (167/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module (TIM)
I/O Registers
NOTE:
Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIM status and control register
(TSC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELS0B and ELS0A are both clear, channel 0 is not connected
to the CLAMP/TCH0 pin. The pin is available as the CLAMP output of
the sync processor.
Table 11-3 shows how ELSxB and ELSxA work. Reset clears the
ELSxB and ELSxA bits.
Table 11-3. Mode, Edge, and Level Selection
MSxB MSxA ELSxB ELSxA
X
0
0
0
X
1
0
0
Mode
Output
Preset
Configuration
Pin is CLAMP of sync processor⁽¹⁾;
Initial Output Level High
Pin is CLAMP of sync processor⁽¹⁾;
Initial Output Level Low
0
0
0
0
0
1
0
0
1
1
Capture on Rising Edge Only
0
Input
Capture
Capture on Falling Edge Only
1
Capture on Rising or Falling Edge
0
1
0
0
1
1
0
1
1
1
Toggle Output on Compare
Output
0
Compare Clear Output on Compare
or PWM
1
Set Output on Compare
1
X
0
1
X
1
1
X
1
1
Buffered Toggle Output on Compare
0
Output
Compare or
Clear Output on Compare
1
Buffered
PWM
Set Output on Compare
Notes:
1. For CLAMP/TCH0 pin only.
NOTE: Before enabling a TIM channel register for input capture operation, make
sure that the TCHx pin is stable for at least two bus clocks.
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
Timer Interface Module (TIM)
Data Sheet
167