EZ80L92MCU Datasheet, PDF (99/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
84
Timer Reload Registers—Low Byte
The Timer Reload Register—Low Byte, detailed in Table 35, stores the least significant
byte (LSB) of the 2-byte timer reload value. In CONTINUOUS mode, the timer reload
value is reloaded into the timer upon end-of-count. When RST_EN (TMRx_CTL[1]) is set
to 1 to enable the automatic reload and restart function, the timer reload value is written to
the timer on the next rising edge of the clock.
Note: The Timer Data registers and Timer Reload registers share the same address
space.
Table 35. Timer Reload Registers—Low Byte (TMR0_RR_L = 0081h, TMR1_RR_L =
0084h, TMR2_RR_L = 0087h, TMR3_RR_L = 008Ah, TMR4_RR_L = 008Dh, or
TMR5_RR_L = 0090h)
Bit
Reset
CPU Access
Note: W = Write only.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Bit
Position
[7:0]
TMRx_RR_L
Value Description
00h–FFh These bits represent the Low byte of the 2-byte timer
reload value, {TMRx_RR_H[7:0], TMRx_RR_L[7:0]}. Bit 7
is bit 7 of the 16-bit timer reload value. Bit 0 is bit 0 (lsb) of
the 16-bit timer reload value.
PS013012-1004
PRELIMINARY
Programmable Reload Timers