EZ80L92MCU Datasheet, PDF (69/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
54
Table 15. Z80 Bus Mode Write States
STATE T1
STATE T2
STATE T3
The Write cycle begins in State T1. The CPU drives the address onto the address bus, the
associated Chip Select signal is asserted.
During State T2, the WR signal is asserted. Depending upon the instruction, either the
MREQ or IORQ signal is asserted. If the external WAIT pin is driven Low at least one
eZ80^® system clock cycle prior to the end of State T2, additional WAIT states (T_WAIT) are
asserted until the WAIT pin is driven High.
During State T3, no bus signals are altered.
Z80 Bus Mode Read and Write timing is illustrated in Figures 7 and 8 . The Z80 Bus
Mode states can be configured for 1 to 15 eZ80^® system clock cycles. In the figures, each
Z80 Bus Mode state is two eZ80^® system clock cycles in duration. Figures 7 and 8 also
illustrate the assertion of 1 WAIT state (T_WAIT) by the external peripheral during each Z80
Bus Mode cycle.
System Clock
T1
T2
T_CLK
T3
ADDR[23:0]
DATA[7:0]
CSx
RD
WAIT
WR
MREQ
or IORQ
Figure 7. Z80 Bus Mode Read Timing Example
PS013012-1004
PRELIMINARY
Chip Selects and Wait States